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  mcf5213 coldfire ? integrated microcontroller reference manual additional devices supported: mcf5211 mcf5212 mcf5213rm rev 1.1 07/2005 ( datasheet : )
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mcf5213 reference manual, rev. 1.1 freescale semiconductor i preliminary paragraph number title page number about this book xxiii audience xxiii organization xxiii conventions xxv register figure conventions xxvi acronyms and abbreviations xxvi terminology conventions xxviii revision history xxx chapter 1 overview 1.1 mcf5213 family confi gurations ................................................................................... 1-2 1.2 block diag ram .............................................................................................................. .. 1-3 1.3 part numbers and packaging .......................................................................................... 1-4 1.4 mcf5213 family feat ures ............................................................................................. 1-4 1.4.1 v2 core overvi ew ...................................................................................................... 1-9 1.4.2 integrated debug module ........................................................................................... 1-9 1.4.3 jtag ..................................................................................................................... .... 1-10 1.4.4 on-chip memori es .................................................. .................................................. 1-10 1.4.4.1 sram ................................................................................................................... 1-10 1.4.4.2 flash .................................................................................................................. .... 1-11 1.4.5 flexcan .................................................................................................................. .1-11 1.4.6 uarts .................................................................................................................... .. 1-11 1.4.7 i 2 c bus ...................................................................................................................... 1-1 1 1.4.8 qspi ..................................................................................................................... ..... 1-11 1.4.9 dma timers (dtim0 -dtim3) ............................................................................... 1-12 1.4.10 general purpose timer (gpta/gptb) .................................................................... 1-12 1.4.11 pulse width modulation timers (pwm) .................................................................. 1-12 1.4.12 periodic interrupt timers (pit0 and pit1) .............................................................. 1-12 1.4.13 software watchdog timer ........................................................................................ 1-13 1.4.14 clock module and phase lo cked loop (pll) ......................................................... 1-13 1.4.15 interrupt controller (intc) ...................................................................................... 1-13 1.4.16 dma controlle r ........................................................................................................ 1- 13 1.4.17 reset ................................................................................................................... ....... 1-13 1.4.18 gpio .................................................................................................................... ..... 1-14 contents
mcf5213 reference manual, rev. 1.1 ii freescale semiconductor preliminary contents paragraph number title page number chapter 2 signal descriptions 2.1 overview ................................................................................................................... ...... 2-1 2.2 reset signa ls .............................................................................................................. ..... 2-5 2.3 pll and clock si gnals ................................................................................................... 2-6 2.4 mode select ion ............................................................................................................. .. 2-6 2.5 external interrupt signals ............................................................................................... 2- 6 2.6 queued serial peripheral interface (qspi) ..................................................................... 2-7 2.7 i 2 c i/o signals ................................................................................................................ 2 -7 2.8 uart module sign als ................................................................................................... 2-8 2.9 dma timer signa ls ........................................................................................................ 2- 8 2.10 adc signals ............................................................................................................... .... 2-8 2.11 general purpose time r signals ...................................................................................... 2-9 2.12 pulse width modulator signals ...................................................................................... 2-9 2.13 debug support signals ................................................................................................... 2- 9 2.14 ezport signal descri ptions .. ......................................................................................... 2-10 2.15 power and ground pi ns .............................................. .................................................. 2-11 chapter 3 coldfire core 3.1 processor pipe lines ........................................................................................................ .3-1 3.2 processor register description ....................................................................................... 3-4 3.2.1 user programming model .......................................................................................... 3-4 3.2.2 data registers (d 0?d7) .............................................................................................. 3-5 3.2.3 address registers (a0?a6) ........................................................................................ 3-5 3.2.4 stack pointers (a7) ..................................................................................................... 3 -5 3.2.5 program counter (pc) ................................................................................................ 3-6 3.2.6 condition code register (ccr) ................................................................................. 3-6 3.2.7 mac register desc ription ......................................................................................... 3-7 3.2.8 supervisor register description ................................................................................. 3-8 3.2.8.1 status register (sr) ................................................................................................ 3-8 3.2.8.2 supervisor/user stack pointe rs (a7 and other_a7) .......................................... 3-9 3.2.8.3 vector base regist er (vbr) ................................................................................ 3-10 3.2.8.4 cache control regist er (cacr) .......................................................................... 3-10 3.2.8.5 access control register s (acr0, acr1) ............................................................ 3-10 3.2.8.6 memory base address register (ram bar, flashbar)-check for cf2 ((condi- tionalized 1 in rambar1 for st/df bcs ki rin does not list the number of the reg- ister. -vg 5/2005)) 3-10 3.3 memory map/register definition ................................................................................ 3-10
mcf5213 reference manual, rev. 1.1 freescale semiconductor iii preliminary contents paragraph number title page number 3.4 additions to the instructi on set architecture ............................................................... 3-11 3.5 exception processing overview ................................................................................... 3-12 3.6 exception stack fram e definition ................................................................................ 3-14 3.7 processor excepti ons .................................................. .................................................. 3-1 5 3.7.1 access error exce ption ............................................................................................ 3-15 3.7.2 address error exce ption ........................................................................................... 3-16 3.7.3 illegal instruction exception ..................................................................................... 3-16 3.7.4 divide-by-ze ro ......................................................................................................... 3- 16 3.7.5 privilege viol ation .................................................................................................... 3- 16 3.7.6 trace except ion ........................................................................................................ 3- 16 3.7.7 unimplemented line-a opcode ............................................................................... 3-17 3.7.8 unimplemented line-f opcode ............................................................................... 3-17 3.7.9 debug interrupt ......................................................................................................... 3 -17 3.7.10 rte and format error exception ............................................................................. 3-17 3.7.11 trap instruction exception ..................................................................................... 3-17 3.7.12 interrupt exception ................................................................................................... 3- 18 3.7.13 fault-on-fault halt ................................................................................................... 3- 18 3.7.14 reset exception ........................................................................................................ 3 -18 3.7.15 reset vect or ............................................................................................................ .. 3-21 3.8 instruction executi on timing ....................................................................................... 3-24 3.8.1 timing assumptions ................................................................................................. 3-24 3.8.2 move instruction exec ution times ........................................................................ 3-25 3.9 standard one operand instruct ion execution ti mes ................................................... 3-26 3.10 standard two operand instru ction execution times ................................................... 3-27 3.11 miscellaneous instruction execution time s ................................................................. 3-28 3.12 mac instruction execution times ch eck cf2 mac (emac #?s) ............................ 3-29 3.13 check cf3/cf2 mac/emacbranch in struction executi on times ........................... 3-30 chapter 4 hardware multiply/accumulate (mac) unit 4.1 overview ................................................................................................................... ...... 4-1 4.1.1 mac programming model ......................................................................................... 4-2 4.1.2 general operat ion ....................................................................................................... 4 -3 4.1.3 mac instruction set summary .................................................................................. 4-4 4.1.4 data represen tation ......... ........................................................................................... 4- 5 4.2 mac instruction execu tion timings ............................................................................. 4-5
mcf5213 reference manual, rev. 1.1 iv freescale semiconductor preliminary contents paragraph number title page number chapter 5 static ram (sram) 5.1 introducti on ............................................................................................................... ...... 5-1 5.1.1 features ................................................................................................................. ...... 5-1 5.1.2 operati on ................................................................................................................ .... 5-1 5.2 register desc ription ....................................................................................................... 5-1 5.2.1 sram base address regi ster (rambar) ............................................................... 5-2 5.2.2 sram initiali zation .................................................................................................... 5- 3 5.2.3 sram initializati on code .......................................................................................... 5-4 5.2.4 power manageme nt .................................................................................................... 5-4 chapter 6 clock module 6.1 features ................................................................................................................... ........ 6-1 6.2 modes of oper ation ........................................................................................................ 6 -1 6.2.1 normal pll m ode .................................................. .................................................... 6-1 6.2.2 1:1 pll m ode ............................................................................................................. 6-1 6.2.3 external clock mode .............................................. .................................................... 6-1 6.3 low-power mode op eration .......................................................................................... 6-2 6.4 block diag ram .............................................................................................................. .. 6-2 6.5 signal descri ptions ........................................................................................................ .6-4 6.5.1 extal .................................................................................................................... ... 6-4 6.5.2 xtal ..................................................................................................................... ..... 6-5 6.5.3 clkout ................................................................................................................... .6-5 6.5.4 clkmod[1:0] ........................................................................................................... 6-5 6.5.5 rsto .......................................................................................................................... 6-5 6.6 memory map and re gisters ............................................................................................ 6-5 6.6.1 module memory map ................................................................................................. 6-5 6.6.2 register descri ptions .................................................................................................. 6- 6 6.6.2.1 synthesizer control regi ster (syncr) ................................................................. 6-6 6.6.2.2 synthesizer status regi ster (synsr) .................................................................... 6-8 6.6.2.3 low power control regi ster (lpcr) ................................................................... 6-10 6.6.3 ppm register desc riptions ....................................................................................... 6-10 6.6.3.1 peripheral power management register high (ppmrh) .................................... 6-11 6.6.3.2 peripheral power management register low (ppmrl) ..................................... 6-12 6.7 functional descri ption .................................................................................................. 6-1 3 6.7.1 system clock m odes .............................................. .................................................. 6-13 6.7.2 clock operation du ring reset .................................................................................. 6-14 6.7.3 system clock ge neration ......................................................................................... 6-14
mcf5213 reference manual, rev. 1.1 freescale semiconductor v preliminary contents paragraph number title page number 6.7.4 pll operation .......................................................................................................... 6- 15 6.7.4.1 phase and frequency de tector (pfd ) ................................................................... 6-15 6.7.4.2 charge pump/loop filter ..................................................................................... 6-16 6.7.4.3 voltage control out put (vco) ............................................................................ 6-16 6.7.4.4 multiplication factor divider (mfd ) ................................................................... 6-16 6.7.4.5 pll lock detect ion ............................................................................................. 6-16 6.7.4.6 pll loss of lock conditions ............................................................................... 6-17 6.7.4.7 pll loss of lock reset ....................................................................................... 6-17 6.7.4.8 loss of clock de tection ....................................................................................... 6-18 6.7.4.9 loss of clock reset .............................................................................................. 6-18 6.7.4.10 alternate clock se lection ..................................................................................... 6-18 6.7.4.11 loss of clock in stop mode ................................................................................. 6-18 chapter 7 power management 7.1 introducti on ............................................................................................................... ...... 7-1 7.1.1 features ................................................................................................................. ...... 7-1 7.2 memory map/register definition .................................................................................. 7-1 7.2.1 wake-up control re gister .......................................................................................... 7-2 7.2.2 peripheral power management set re gisters (ppmsr0 & ppmsr1) ...................... 7-3 7.2.3 peripheral power management clear registers (ppmcr0 & ppmcr1) .................. 7-4 7.2.4 peripheral power ma nagement registers (ppmhr0 & ppmlr0) 7-4 7.2.5 low-power control regi ster (lpcr) ........................................................................ 7-6 7.2.6 miscellaneous control re gister (misccr) ............................................................... 7-7 7.3 functional descri ption .................................................................................................... 7 -8 7.3.1 peripheral shut down ................................................................................................. 7-8 7.3.2 limp mode ................................................................................................................ .7-8 7.3.3 low-power mode s ...................................................................................................... 7-8 7.3.3.1 run mode ............................................................................................................... 7-9 7.3.3.2 wait mode .............................................................................................................. 7-9 7.3.3.3 doze mode .............................................................................................................. 7-9 7.3.3.4 stop mode .............................................................................................................. .7-9 7.3.4 peripheral behavior in low-power modes .............................................................. 7-10 7.3.4.1 coldfire core ....................................................................................................... 7-1 0 7.3.4.2 static random-access me mory (sram) ............................................................ 7-10 7.3.4.3 clock module ....................................................................................................... 7-10 7.3.4.4 chip configurati on module .................................................................................. 7-10 7.3.4.5 reset controll er .................................................................................................... 7-1 0 7.3.4.6 system control m odule (scm) ............................................................................ 7-11
mcf5213 reference manual, rev. 1.1 vi freescale semiconductor preliminary contents paragraph number title page number 7.3.4.7 gpio ports ............................................................................................................ 7 -11 7.3.4.8 interrupt controllers (intc0) .............................................................................. 7-11 7.3.4.9 edge port .............................................................................................................. 7-11 7.3.4.10 dma controller .................................................................................................... 7-12 7.3.4.11 on-chip watchdog timer ..................................................................................... 7-12 7.3.4.12 programmable interrupt timers (p it0, pit1, pit2 and pit3) ............................ 7-12 7.3.4.13 dma timers (dtim 0?dtim3) ........................................................................... 7-12 7.3.4.14 queued serial peripheral interface (qspi) ........................................................... 7-13 7.3.4.15 uart modules (uart0, uart1, and uart2) ............................................... 7-13 7.3.4.16 i2c module ........................................................................................................... 7 -13 7.3.4.17 jtag .................................................................................................................. ... 7-13 7.3.4.18 bdm ................................................................................................................... .. 7-13 7.3.5 summary of peripheral state during low-power modes ........................................ 7-14 chapter 8 chip configuration module (ccm) 8.1 introducti on ............................................................................................................... ...... 8-1 8.1.1 block diag ram ............................................................................................................ 8-1 8.1.2 features ................................................................................................................. ...... 8-1 8.2 external signal desc riptions .......................................................................................... 8-2 8.2.1 rcon ......................................................................................................................... 8-2 8.2.2 clkmod[1:0] ........................................................................................................... 8-2 8.3 memory map/register definition .................................................................................. 8-2 8.3.1 programming m odel ................................................................................................... 8-2 8.3.2 memory map .............................................................................................................. 8 -3 8.3.3 register descri ptions .................................................................................................. 8- 3 8.3.3.1 chip configuration re gister (ccr ) ....................................................................... 8-3 8.3.3.2 reset configuration regi ster (rcon) ................................................................... 8-4 8.3.3.3 chip identification re gister (cir) ......................................................................... 8-5 8.4 functional descri ption .................................................................................................... 8 -5 8.4.1 reset configur ation .................................................................................................... 8- 6 8.4.2 output pad strength c onfiguration ............................................................................ 8-7 8.4.3 clock mode sel ection ................................................................................................. 8-7 8.5 reset ...................................................................................................................... .......... 8-7 chapter 9 reset controller module 9.1 features ................................................................................................................... ........ 9-1
mcf5213 reference manual, rev. 1.1 freescale semiconductor vii preliminary contents paragraph number title page number 9.2 block diag ram .............................................................................................................. .. 9-1 9.3 signals .................................................................................................................... ......... 9-2 9.3.1 rsti ............................................................................................................................ 9- 2 9.3.2 rsto .......................................................................................................................... 9-2 9.4 memory map and re gisters ............................................................................................ 9-2 9.4.1 reset control regist er (rcr) .................................................................................... 9-2 9.4.2 reset status regist er (rsr) ....................................................................................... 9-3 9.5 functional descri ption .................................................................................................... 9 -4 9.5.1 reset sources ............................................................................................................ .. 9-4 9.5.1.1 power-on rese t ...................................................................................................... 9-5 9.5.1.2 external re set ......................................................................................................... 9-5 9.5.1.3 loss-of-clock re set ............................................................................................... 9-5 9.5.1.4 loss-of-lock re set ............................................. .................................................... 9-6 9.5.1.5 software re set ........................................................................................................ 9 -6 9.5.1.6 lvd reset .............................................................................................................. 9-6 9.5.2 reset control flow ..................................................................................................... 9- 6 9.5.2.1 synchronous reset requests .................................................................................. 9-8 9.5.2.2 internal reset re quest ........................................ .................................................... 9-8 9.5.2.3 power-on reset/low-voltage detect reset .......................................................... 9-8 9.5.3 concurrent re sets ....................................................................................................... 9 -8 9.5.3.1 reset flow ............................................................................................................. .9-8 9.5.3.2 reset status flags ................................................................................................... 9- 9 chapter 10 system control module (scm) 10.1 overview .................................................................................................................. ..... 10-1 10.2 features .................................................................................................................. ....... 10-1 10.3 memory map and regist er definition .......................................................................... 10-2 10.4 register descri ptions .................................................................................................... 1 0-2 10.4.1 internal peripheral system base address register (ipsbar) ................................. 10-2 10.4.2 memory base address regi ster (rambar) .......................................................... 10-3 10.4.3 core reset status regi ster (crsr) .......................................................................... 10-5 10.4.4 core watchdog control regi ster (cwcr) .............................................................. 10-6 10.4.5 core watchdog service regi ster (cwsr) ............................................................... 10-8 10.5 internal bus arbi tration ................................................................................................ 10 -8 10.5.1 overview ................................................................................................................ ... 10-8 10.5.2 arbitration algor ithms ............................................................................................. 10-9 10.5.2.1 round-robin mode .............................................................................................. 10-9 10.5.2.2 fixed mode ........................................................................................................... 1 0-9 10.5.3 bus master park regi ster (mpark) ...................................................................... 10-10
mcf5213 reference manual, rev. 1.1 viii freescale semiconductor preliminary contents paragraph number title page number 10.6 system access control unit (sacu) ......................................................................... 10-11 10.6.1 overview ................................................................................................................ . 10-12 10.6.2 features ................................................................................................................ ... 10-12 10.6.3 memory map/register definition .......................................................................... 10-14 10.6.3.1 master privilege regi ster (mpr) ....................................................................... 10-14 10.6.3.2 peripheral access control regi sters (pacr0?pacr8) .................................... 10-15 10.6.3.3 grouped peripheral access control re gisters (gpacr0 & gpacr1) ............ 10-16 chapter 11 general purpose i/o module 11.1 introducti on .............................................................................................................. ..... 11-1 11.2 overview .................................................................................................................. ..... 11-2 11.3 features .................................................................................................................. ....... 11-2 11.4 signal descri ptions ....................................................................................................... 11-2 11.5 memory map/register definition ................................................................................ 11-3 11.5.1 ports memory map ................................................................................................... 11-3 11.6 register descri ptions .................................................................................................... 1 1-4 11.6.1 port output data regi sters (portn) ....................................................................... 11-4 11.6.2 port data direction re gisters (ddrn) ..................................................................... 11-6 11.6.3 port pin data/set data regi sters (portnp/setn ) ................................................. 11-8 11.6.4 port clear output data registers (clrn) .............................................................. 11-10 11.6.5 pin assignment re gisters ....................................................................................... 11-11 11.6.5.1 dual function pin assignm ent registers ........................................................... 11-11 11.6.5.2 quad function pin assignm ent registers .......................................................... 11-12 11.6.5.3 port nq pin assignmen t register ...................................................................... 11-13 11.6.6 pad control regi sters ............................................. ................................................ 11-13 11.6.6.1 pin slew rate re gister ....................................................................................... 11-13 11.6.6.2 pin drive strength register ................................................................................ 11-13 11.7 ports interrupts .......................................................................................................... .. 11-14 chapter 12 interrupt controller module 12.1 68k/coldfire interrupt arch itecture overvi ew ........................................................... 12-1 12.1.1 interrupt controller theo ry of operation ................................................................. 12-2 12.1.1.1 interrupt recogni tion ............................................................................................ 12-3 12.1.1.2 interrupt prioriti zation ........................................ .................................................. 12-3 12.1.1.3 interrupt vector de termination ............................................................................ 12-3 12.2 memory map ................................................................................................................ 12-4
mcf5213 reference manual, rev. 1.1 freescale semiconductor ix preliminary contents paragraph number title page number 12.3 register descri ptions .................................................................................................... 1 2-5 12.3.1 interrupt pending register s (iprhn, iprln) ........................................................... 12-5 12.3.2 interrupt mask register (imrhn, imrln) .............................................................. 12-6 12.3.3 interrupt force registers (intfrchn, intfrcln) ............................................... 12-8 12.3.4 interrupt request level re gister (irlrn) ............................................................. 12-10 12.3.5 interrupt acknowledge le vel and priority regist er (iacklprn) ........................ 12-10 12.3.6 interrupt control register (icrnx, (x = 1, 2,..., 63)) .............................................. 12-11 12.3.6.1 interrupt sour ces ................................................. ................................................ 12-1 1 12.3.7 software and level n iack register s (swiackr, l1iack?l7iack) ............. 12-14 12.4 low-power wakeup operation .................................................................................. 12-15 chapter 13 edge port module (eport) 13.1 introducti on .............................................................................................................. ..... 13-1 13.2 low-power mode op eration ........................................................................................ 13-1 13.3 interrupt/general-purpose i/o pin descripti ons ........................................................... 13-2 13.4 memory map and re gisters .......................................................................................... 13-3 13.4.1 memory map ............................................................................................................ 13 -3 13.4.2 register s ............................................................................................................... ..... 13-3 13.4.2.1 eport pin assignment regi ster (eppar) ......................................................... 13-3 13.4.2.2 eport data direction re gister (epddr) .......................................................... 13-4 13.4.2.3 edge port interrupt enable register (epi er) ...................................................... 13-5 13.4.2.4 edge port data regi ster (epdr) .......................................................................... 13-5 13.4.2.5 edge port pin data re gister (eppdr) ................................................................. 13-6 13.4.2.6 edge port flag regi ster (epfr) ........................................................................... 13-6 chapter 14 dma controller module 14.1 overview .................................................................................................................. ..... 14-1 14.1.1 dma module featur es ........................................... .................................................. 14-2 14.2 dma transfer over view ............................................ .................................................. 14-3 14.3 dma controller module pr ogramming model ............................................................ 14-3 14.3.1 source address register s (sar0?sar3) ................................................................ 14-4 14.3.2 destination address regist ers (dar0?dar3) ....................................................... 14-5 14.3.3 byte count registers (bcr0?bcr3) ...................................................................... 14-5 14.3.4 dma control registers (dcr0?dcr3) .................................................................. 14-5 14.3.5 dma status registers (dsr0?dsr3) ..................................................................... 14-8 14.4 dma controller module func tional description ........................................................ 14-8
mcf5213 reference manual, rev. 1.1 x freescale semiconductor preliminary contents paragraph number title page number 14.4.1 transfer requests (cycle-steal and continuous modes) ......................................... 14-9 14.4.2 data transfer modes ................................................................................................ 14-9 14.4.2.1 dual-address tran sfers ........................................................................................ 14-9 14.4.3 channel initialization and startup .......................................................................... 14-10 14.4.3.1 channel prioritiz ation ......................................................................................... 14-10 14.4.3.2 programming the dma cont roller module ....................................................... 14-10 14.4.4 data transfer .......................................................................................................... 1 4-11 14.4.4.1 auto-alignment .................................................................................................. 14-11 14.4.4.2 bandwidth cont rol .............................................. ................................................ 14-11 14.4.5 termination ............................................................................................................. 14-11 chapter 15 coldfire flash module (cfm) 15.1 features .................................................................................................................. ....... 15-1 15.2 block diag ram ............................................................................................................. . 15-2 15.3 memory map ................................................................................................................ 15-4 15.3.1 cfm configurati on field ......................................................................................... 15-5 15.3.2 flash base address regist er (flashbar) ............................................................ 15-5 15.3.3 cfm registers .......................................................................................................... 1 5-7 15.3.4 register descri ptions ................................................................................................ 15- 8 15.3.4.1 cfm configuration regi ster (cfmcr) ............................................................... 15-8 15.3.4.2 cfm clock divider regist er (cfmclkd) ......................................................... 15-9 15.3.4.3 cfm security register (cfmsec) .................................................................... 15-10 15.3.4.4 cfm protection register (cfmprot) .............................................................. 15-11 15.3.4.5 cfm supervisor access re gister (cfmsacc) ................................................ 15-12 15.3.4.6 cfm data access regist er (cfmdacc) ......................................................... 15-13 15.3.4.7 cfm user status regist er (cfmustat) ......................................................... 15-14 15.3.4.8 cfm command register (cfmcmd) ............................................................... 15-15 15.4 cfm operation ........................................................................................................... 15 -16 15.4.1 read operati ons ...................................................................................................... 15- 16 15.4.2 write operati ons ..................................................................................................... 15- 16 15.4.3 program and erase op erations ............................................................................... 15-17 15.4.3.1 setting the cfmclkd register ........................................................................ 15-17 15.4.3.2 program, erase, and ve rify sequences ............................................................... 15-18 15.4.3.3 flash valid commands ....................................................................................... 15-19 15.4.3.4 flash user mode illegal operations ................................................................... 15-21 15.4.4 stop mode ............................................................................................................... 15-21 15.5 flash security op eration ............................................................................................ 15-22 15.5.1 back door ac cess ................................................................................................... 15-23 15.5.2 erase verify ch eck ................................................. ................................................ 15-23
mcf5213 reference manual, rev. 1.1 freescale semiconductor xi preliminary contents paragraph number title page number 15.6 reset ..................................................................................................................... ....... 15-23 15.7 interrupts ................................................................................................................ ..... 15-23 chapter 16 ezport 16.1 features .................................................................................................................. ....... 16-1 16.2 modes of oper ation ...................................................................................................... 16 -1 16.3 external signal desc ription .......................................................................................... 16-2 16.3.1 overview ................................................................................................................ ... 16-2 16.3.2 detailed signal desc riptions .................................................................................... 16-2 16.3.2.1 ezpck ? ezport clock ...................................................................................... 16-2 16.3.2.2 ezpcs ? ezport chip select .............................................................................. 16-3 16.3.2.3 ezpd ? ezport serial data in ............................................................................ 16-3 16.3.2.4 ezpq ? ezport serial data out .......................................................................... 16-3 16.4 command definition .................................................................................................... 16-3 16.4.1 command descrip tions ........................................... .................................................. 16-4 16.4.1.1 write enable ......................................................................................................... 1 6-4 16.4.1.2 write disabl e ........................................................................................................ 1 6-4 16.4.1.3 read status regi ster ............................................................................................. 16-4 16.4.1.4 write configuration register ............................................................................... 16-5 16.4.1.5 read data ............................................................................................................. . 16-6 16.4.1.6 read data at high speed ...................................................................................... 16-6 16.4.1.7 page program ........................................................................................................ 16 -6 16.4.1.8 sector er ase .......................................................................................................... 16-6 16.4.1.9 bulk erase ............................................................................................................ . 16-7 16.4.1.10 reset chip ........................................................................................................... .. 16-7 16.5 functional descri ption .................................................................................................. 16 -7 16.6 initialization/applicati on informati on .......................................................................... 16-7 chapter 17 programmable interrupt ti mer modules (pit0?pit1) 17.1 introducti on .............................................................................................................. ..... 17-1 17.1.1 overview ................................................................................................................ ... 17-1 17.1.2 block diagra m .......................................................................................................... 1 7-1 17.1.3 low-power mode op eration .................................................................................... 17-1 17.2 memory map/register definition ................................................................................ 17-2 17.2.1 pit control and status register (pcsr n ) ................................................................ 17-3 17.2.2 pit modulus register (pmr n ) ................................................................................. 17-5
mcf5213 reference manual, rev. 1.1 xii freescale semiconductor preliminary contents paragraph number title page number 17.2.3 pit count register (pcntr n ) ................................................................................. 17-5 17.3 functional descri ption .................................................................................................. 17 -5 17.3.1 set-and-forget time r operation ............................................................................... 17-6 17.3.2 free-running timer op eration ................................................................................ 17-6 17.3.3 timeout specifica tions ............................................................................................. 17-6 17.3.4 interrupt oper ation ................................................................................................... 17 -7 chapter 18 general purpose timer module (gpt) 18.1 introducti on .............................................................................................................. ..... 18-1 18.2 features .................................................................................................................. ....... 18-1 18.3 block diag ram ............................................................................................................. . 18-2 18.4 low-power mode op eration ........................................................................................ 18-3 18.5 signal descri ption ........................................................................................................ . 18-3 18.5.1 gpt[2:0] ................................................................................................................ ... 18-3 18.5.2 gpt3 .................................................................................................................... ..... 18-3 18.5.3 syncn ................................................................................................................... ... 18-4 18.6 memory map and re gisters .......................................................................................... 18-4 18.6.1 gpt input capture/output compare select register (gptios) ............................. 18-5 18.6.2 gpt compare force regist er (gpcforc) ............................................................. 18-6 18.6.3 gpt output compare 3 mask register (gptoc3m) .............................................. 18-6 18.6.4 gpt output compare 3 data register (gpt oc3d) ................................................ 18-7 18.6.5 gpt counter register (gptcnt) ........................................................................... 18-7 18.6.6 gpt system control regist er 1 (gptscr1) ........................................................... 18-8 18.6.7 gpt toggle-on-overflow re gister (gpttov) ...................................................... 18-9 18.6.8 gpt control register 1 (gptctl1) ........................................................................ 18-9 18.6.9 gpt control register 2 (gptctl2) ...................................................................... 18-10 18.6.10 gpt interrupt enable re gister (gptie) ................................................................ 18-10 18.6.11 gpt system control regist er 2 (gptscr2) ......................................................... 18-11 18.6.12 gpt flag register 1 (gptflg1) ........................................................................... 18-12 18.6.13 gpt flag register 2 (gptflg2) ........................................................................... 18-12 18.6.14 gpt channel register s (gptcn) ........................................................................... 18-13 18.6.15 pulse accumulator control re gister (gptpactl) .............................................. 18-14 18.6.16 pulse accumulator flag regi ster (gptpafl g) .................................................... 18-15 18.6.17 pulse accumulator counter re gister (gptpacnt) ............................................. 18-16 18.6.18 gpt port data regist er (gptport ) ..................................................................... 18-16 18.6.19 gpt port data direction re gister (gptdd r) ....................................................... 18-17 18.7 functional descri ption ................................................................................................ 18-1 7 18.7.1 prescaler ............................................................................................................... ... 18-17 18.7.2 input captur e .......................................................................................................... 1 8-17
mcf5213 reference manual, rev. 1.1 freescale semiconductor xiii preliminary contents paragraph number title page number 18.7.3 output compar e ...................................................................................................... 18-1 8 18.7.4 pulse accumula tor .................................................................................................. 18-18 18.7.5 event counter m ode ............................................................................................... 18-18 18.7.6 gated time accumulation mode ........................................................................... 18-19 18.7.7 general-purpose i/ o ports ...................................................................................... 18-20 18.8 reset ..................................................................................................................... ....... 18-22 18.9 interrupts ................................................................................................................ ..... 18-22 18.9.1 gpt channel interr upts (cnf) ............................................................................... 18-22 18.9.2 pulse accumulator over flow (paovf) ................................................................. 18-22 18.9.3 pulse accumulator i nput (paif) ............................................................................ 18-23 18.9.4 timer overflow (tof) ........................................................................................... 18-23 chapter 19 dma timers (dtim0?dtim3) 19.1 introducti on .............................................................................................................. ..... 19-1 19.1.1 overview ................................................................................................................ ... 19-1 19.1.2 features ................................................................................................................ ..... 19-2 19.2 memory map/register definition ................................................................................ 19-2 19.2.1 prescaler ............................................................................................................... ..... 19-2 19.2.2 capture mode ........................................................................................................... 1 9-3 19.2.3 reference comp are ................................................................................................... 19-3 19.2.4 output m ode ............................................................................................................. 19-3 19.2.5 memory map ............................................................................................................ 19 -3 19.2.6 dma timer mode registers (dtmr n ) ................................................................... 19-4 19.2.7 dma timer extended mode registers (dtxmr n ) ................................................ 19-5 19.2.8 dma timer event registers (dter n ) .................................................................... 19-6 19.2.9 dma timer reference registers (dtrr n ) ............................................................. 19-7 19.2.10 dma timer capture registers (dtcr n ) ................................................................ 19-8 19.2.11 dma timer counters (dtcn n ) .............................................................................. 19-8 19.3 initialization/applicati on informati on .......................................................................... 19-9 19.3.1 code example ........................................................................................................... 1 9-9 19.3.2 calculating time-out values ................................................................................. 19-10 chapter 20 queued serial peripheral interface (qspi) 20.1 introducti on .............................................................................................................. ..... 20-1 20.1.1 block diagra m .......................................................................................................... 2 0-1 20.1.2 overview ................................................................................................................ ... 20-2
mcf5213 reference manual, rev. 1.1 xiv freescale semiconductor preliminary contents paragraph number title page number 20.1.3 features ................................................................................................................ ..... 20-2 20.1.4 external signals de scription .................................................................................... 20-2 20.1.5 modes of operat ion .................................................................................................. 20-3 20.2 memory map/register definition ................................................................................ 20-3 20.2.1 qspi mode regist er (qmr) .................................................................................... 20-3 20.2.2 qspi delay register (qdlyr) ............................................................................... 20-5 20.2.3 qspi wrap regist er (qwr) ..................................................................................... 20-6 20.2.4 qspi interrupt regi ster (qir) .................................................................................. 20-6 20.2.5 qspi address regist er (qar) ................................................................................. 20-8 20.2.6 qspi data regist er (qdr) ....................................................................................... 20-8 20.2.7 command ram registers (qcr0?qcr15) ............................................................ 20-8 20.3 functional descri ption ................................................................................................ 20-1 0 20.3.1 qspi ram .............................................................................................................. 20 -11 20.3.1.1 receive ram ..................................................................................................... 20-12 20.3.1.2 transmit ram .................................................................................................... 20-12 20.3.1.3 command ram .................................................................................................. 20-13 20.3.2 baud rate select ion ................................................................................................ 20-13 20.3.3 transfer delays ....................................................................................................... 20 -14 20.3.4 transfer length ....................................................................................................... 20 -15 20.3.5 data transfer .......................................................................................................... 2 0-15 20.3.6 initialization/applicati on information .................................................................... 20-16 chapter 21 uart modules 21.1 introducti on .............................................................................................................. ..... 21-1 21.1.1 overview ................................................................................................................ ... 21-1 21.1.2 features ................................................................................................................ ..... 21-2 21.2 external signal desc ription .......................................................................................... 21-3 21.3 memory map/register definition ................................................................................ 21-4 21.3.1 uart mode registers 1 (umr1 n ) ......................................................................... 21-5 21.3.2 uart mode register 2 (umr2 n ) ........................................................................... 21-6 21.3.3 uart status registers (usr n ) ............................................................................... 21-8 21.3.4 uart clock select registers (ucsr n ) .................................................................. 21-9 21.3.5 uart command registers (ucr n ) ...................................................................... 21-10 21.3.6 uart receive buffers (urb n ) ............................................................................. 21-12 21.3.7 uart transmit buffers (utb n ) ........................................................................... 21-13 21.3.8 uart input port change registers (uipcr n ) ...................................................... 21-13 21.3.9 uart auxiliary cont rol register (uacr n ) ......................................................... 21-14 21.3.10 uart interrupt status /mask registers (uisr n /uimr n ) ..................................... 21-14 21.3.11 uart baud rate generator registers (ubg1 n /ubg2 n ) ..................................... 21-16
mcf5213 reference manual, rev. 1.1 freescale semiconductor xv preliminary contents paragraph number title page number 21.3.12 uart input port register (uip n ) .......................................................................... 21-17 21.3.13 uart output port command registers (uop1 n /uop0 n ) ................................... 21-17 21.4 functional descri ption ................................................................................................ 21-1 8 21.4.1 transmitter/receiver clock source ........................................................................ 21-18 21.4.1.1 programmable di vider ........................................................................................ 21-18 21.4.1.2 calculating baud rates ....................................................................................... 21-19 21.4.1.2.1 internal bus cloc k baud rates ....................................................................... 21-19 21.4.1.2.2 external cl ock ................................................................................................ 21-19 21.4.2 transmitter and receiver operating mode s ........................................................... 21-19 21.4.2.1 transmitter .......................................................................................................... 2 1-20 21.4.2.2 receiver .............................................................................................................. 21-21 21.4.2.3 fifo .................................................................................................................. .. 21-22 21.4.3 looping modes ....................................................................................................... 21-2 3 21.4.3.1 automatic echo m ode ........................................................................................ 21-24 21.4.3.2 local loop-back mode ...................................................................................... 21-24 21.4.3.3 remote loop-back mode ................................................................................... 21-24 21.4.4 multidrop mode ...................................................................................................... 21-2 5 21.4.5 bus operati on ......................................................................................................... 21 -27 21.4.5.1 read cycles ........................................................................................................ 21- 27 21.4.5.2 write cycles ....................................................................................................... 21- 27 21.4.6 programmi ng .......................................................................................................... 21- 27 21.4.6.1 interrupt and dma request initializati on .......................................................... 21-27 21.4.6.1.1 setting up the uart to gene rate core interrupts ......................................... 21-27 21.4.6.1.2 setting up the uart to request dma service ............................................. 21-28 21.4.6.2 uart module initializa tion sequence .............................................................. 21-29 chapter 22 i 2 c interface 22.1 introducti on .............................................................................................................. ..... 22-1 22.2 overview .................................................................................................................. ..... 22-1 22.3 features .................................................................................................................. ....... 22-1 22.4 i 2 c system configur ation ............................................................................................. 22-3 22.4.1 start signal ........................................................................................................... 2 2-3 22.4.2 slave address tran smission ..................................................................................... 22-4 22.4.3 data transfer ........................................................................................................... . 22-4 22.4.4 acknowledge ............................................................................................................ 2 2-4 22.4.5 stop signal ............................................................................................................. 22-5 22.4.6 repeated start ...................................................................................................... 22-5 22.4.7 clock synchronization a nd arbitration .................................................................... 22-6 22.4.8 handshaking and clock stretching ........................................................................... 22-7
mcf5213 reference manual, rev. 1.1 xvi freescale semiconductor preliminary contents paragraph number title page number 22.5 memory map/register definition ................................................................................ 22-8 22.5.1 i 2 c address register (i2adr) ................................................................................. 22-8 22.5.2 i 2 c frequency divider regi ster (i2fdr) ................................................................. 22-9 22.5.3 i 2 c control register (i2cr) ................................................................................... 22-10 22.5.4 i 2 c status register (i2sr) ...................................................................................... 22-11 22.5.5 i 2 c data i/o register (i2dr) ................................................................................. 22-12 22.6 i 2 c programming exam ples ....................................................................................... 22-12 22.6.1 initialization se quence ............................................................................................ 22-12 22.6.2 generation of st art ............................................................................................. 22-13 22.6.3 post-transfer softwa re response ........................................................................... 22-13 22.6.4 generation of st op ................................................................................................ 22-14 22.6.5 generation of repeat ed start ............................................................................. 22-15 22.6.6 slave mode ............................................................................................................. 2 2-15 22.6.7 arbitration lo st ....................................................................................................... 2 2-15 chapter 23 analog-to-digital converter (adc) 23.1 introducti on .............................................................................................................. ..... 23-1 23.2 features .................................................................................................................. ....... 23-1 23.3 block diag ram ............................................................................................................. . 23-1 23.4 functional descri ption .................................................................................................. 23 -2 23.4.1 input mux func tion ................................................................................................ 23-5 23.4.2 adc sample conve rsion .......................................................................................... 23-6 23.4.2.1 single-ended samp les .......................................................................................... 23-7 23.4.2.2 differential sa mples ............................................................................................. 23-8 23.4.3 adc data proce ssing ............................................................................................... 23-9 23.4.4 sequential vs. parall el sampling ............................................................................ 23-10 23.4.5 scan sequenci ng ..................................................................................................... 23-1 1 23.4.6 power manageme nt ................................................................................................ 23-12 23.4.6.1 power management modes ................................................................................ 23-12 23.4.6.2 power management details ................................................................................ 23-13 23.4.6.3 adc stop mode of operation ......................................................................... 23-14 23.4.7 adc clock ............................................................................................................. 23 -14 23.4.7.1 general ............................................................................................................... . 23-14 23.4.7.2 description of cloc k operation .......................................................................... 23-15 23.4.7.3 adc clock resynchronization at start of scan ................................................. 23-15 23.4.8 voltage reference pins vrefh& vrefl ........................................................... 23-17 23.4.9 supply pins vdda and vssa ............................................................................... 23-18 23.5 register defini tions .................................................................................................... 23 -18 23.5.1 control 1 register (ctrl1) ................................................................................... 23-21
mcf5213 reference manual, rev. 1.1 freescale semiconductor xvii preliminary contents paragraph number title page number 23.5.1.1 reserved?bit 15 ................................................................................................ 23-21 23.5.1.2 stop 0 (stop0)?bit 14 .................................................................................. 23-22 23.5.1.3 start conversion (sta rt0)?bit 13 ................................................................. 23-22 23.5.1.4 synchronization 0 enable (sync0)?bit 12 ..................................................... 23-22 23.5.1.5 end of scan interrupt enab le 0 (eosie0)?bit 11 ........................................... 23-22 23.5.1.6 zero crossing interrupt en able (zcie)?bit 10 ................................................ 23-22 23.5.1.7 low limit interrupt enable (llmtie)?bit 9 .................................................. 23-23 23.5.1.8 high limit interrupt enable (hlmtie)?bit 8 ................................................. 23-23 23.5.1.9 channel configure (c hncfg)?bits 7?4 ....................................................... 23-23 23.5.1.10 scan mode control (smo de)?bits 2-0 ........................................................... 23-24 23.5.2 control 2 register (ctrl2) unde r sequential scan modes ................................. 23-25 23.5.2.1 reserved?bits 15?5 .......................................................................................... 23-26 23.5.2.2 clock divisor select (div)?bits 4?0 ............................................................... 23-26 23.5.3 control 2 register (ctrl2) unde r parallel scan modes ...................................... 23-26 23.5.3.1 reserved?bit 15 ................................................................................................ 23-27 23.5.3.2 stop (stop1)?bi t 14 ........................................................................................ 23-27 23.5.3.3 start conversion (sta rt1)?bit 13 ................................................................. 23-27 23.5.3.4 sync1 enable (sync 1)?bit 12 ..................................................................... 23-27 23.5.3.5 reserved?bits 10?6 .......................................................................................... 23-27 23.5.3.6 end of scan interrupt enab le 1 (eosie1)?bit 11 ........................................... 23-28 23.5.3.7 simultaneous mode (s imult)?bit 5 .............................................................. 23-28 23.5.3.8 clock divisor select (div)?bits 4?0 ............................................................... 23-28 23.5.4 zero crossing control regi ster (zxctrl) ........................................................... 23-29 23.5.4.1 zero crossing enable n (zcen)?bits 15?0 ...................................................... 23-29 23.5.5 channel list 1 and 2 registers (clst1 and clst2) ............................................ 23-29 23.5.5.1 reserved?bits 15, 11, 7 and 3 .......................................................................... 23-30 23.5.5.2 sample n (sample4)?bits 2, 1, and 0 ........................................................ 23-30 23.5.6 sample disable regist er (sdis) ............................................................................. 23-31 23.5.6.1 reserved?bits 15?8 .......................................................................................... 23-31 23.5.6.2 disable sample (dsn )?bits 7?0 ....................................................................... 23-31 23.5.7 status register (stat) ........................................................................................... 23-31 23.5.7.1 conversion in progress 0 (cip0)?bit 15 .......................................................... 23-32 23.5.7.2 conversion in progress 1 (cip1)?bit 14 .......................................................... 23-32 23.5.7.3 reserved?bit 13 ................................................................................................ 23-32 23.5.7.4 end of scan interrupt 1 (eosi1)?bit 12 .......................................................... 23-32 23.5.7.5 end of scan interrupt 0 (eosi0)?bit 11 .......................................................... 23-33 23.5.7.6 zero crossing interrupt (zci)?bit 10 ............................................................... 23-33 23.5.7.7 low limit interrupt ( llmti)?bit 9 ................................................................ 23-33 23.5.7.8 high limit interrupt (h lmti)?bit 8 ............................................................... 23-33 23.5.7.9 ready sample 7?0 (rdy n)?bits 7?0 ............................................................... 23-34 23.5.8 limit status register (limstat) ......................................................................... 23-34
mcf5213 reference manual, rev. 1.1 xviii freescale semiconductor preliminary contents paragraph number title page number 23.5.9 zero crossing status regi ster (zxstat) .............................................................. 23-35 23.5.9.1 reserved?bits 15?8 .......................................................................................... 23-35 23.5.9.2 zero crossing status (z cs[7:0])?bits 7?0 ....................................................... 23-35 23.5.10 result 0-7 register s (rslt0?7) ............................................................................. 23-36 23.5.10.1 sign extend (sex t)?bit 15 ............................................................................. 23-36 23.5.10.2 digital result of the c onversion (rslt)?bits 14?3 ....................................... 23-36 23.5.10.3 test data (test_da ta)?bits 14?3 ..................................................................... 23-37 23.5.10.4 reserved?bit s 2?0 ............................................................................................ 23-37 23.5.11 low and high limit registers (l olim0-7 and hili m0-7) ................................. 23-37 23.5.12 offset registers (offst0?7) ................................................................................. 23-38 23.5.13 power control regist er (pwr) .............................................................................. 23-39 23.5.13.1 auto standby (asb )?bit 15 ............................................................................. 23-40 23.5.13.2 reserved?bit s 14?13 ........................................................................................ 23-40 23.5.13.3 voltage reference power st atus 2 (psts2)?bit 12 ......................................... 23-40 23.5.13.4 converter b power status 1 (psts1)?bi t 11 ................................................... 23-40 23.5.13.5 converter a power status 0 (psts0)?bi t 10 ................................................... 23-40 23.5.13.6 power-up delay (pud elay)?bits 9?4 .......................................................... 23-40 23.5.13.7 auto power-down (apd)?bit 3 ...................................................................... 23-41 23.5.13.8 power-down control for voltage re ference circuit 2 (pd2)?bit 2 ............... 23-41 23.5.13.9 manual power-down for conve rter b (pd1)?bit 1 ......................................... 23-41 23.5.13.10 manual power-down for conve rter a (pd0)?bit 0 ......................................... 23-42 23.5.14 voltage reference regi ster (vref) ...................................................................... 23-42 23.5.14.1 select vrefh source (s el_vrefh)?bit 15 ................................................. 23-42 23.5.14.2 select vrefl source (s el_vrefl)?bit 14 ................................................. 23-42 23.5.14.3 reserved?bit s 13?0 .......................................................................................... 23-43 chapter 24 pulse width modula tion (pwm) module 24.1 introducti on .............................................................................................................. ..... 24-1 24.1.1 overview ................................................................................................................ ... 24-1 24.2 memory map/register definition ................................................................................ 24-2 24.2.1 pwm enable register (pwme) ............................................................................... 24-3 24.2.2 pwm polarity register (pwmpol) ........................................................................ 24-4 24.2.3 pwm clock select regist er (pwmclk) ................................................................ 24-4 24.2.4 pwm prescale clock select register (pwmprclk) ............................................. 24-5 24.2.5 pwm center align enable re gister (pwmcae) ................................................... 24-6 24.2.6 pwm control register (pwmctl) ......................................................................... 24-7 24.2.7 pwm scale a register (pwmscla) ...................................................................... 24-8 24.2.8 pwm scale b register (pwmsclb) ...................................................................... 24-8 24.2.9 pwm channel counter registers (pwmcnt n ) ..................................................... 24-9
mcf5213 reference manual, rev. 1.1 freescale semiconductor xix preliminary contents paragraph number title page number 24.2.10 pwm channel period registers (pwmper n ) ...................................................... 24-10 24.2.11 pwm channel duty regist ers (pwmdtyn) ........................................................ 24-11 24.2.12 pwm shutdown register (pwmsdn) .................................................................. 24-11 24.3 functional descri ption ................................................................................................ 24-1 2 24.3.1 pwm clock sel ect .................................................. ................................................ 24-12 24.3.1.1 prescaled clock (a or b) .................................................................................... 24-13 24.3.1.2 scaled clock (sa or sb) .................................................................................... 24-14 24.3.1.3 clock select ........................................................................................................ 24 -14 24.3.2 pwm channel time rs ............................................................................................ 24-14 24.3.2.1 pwm enable ....................................................................................................... 24-15 24.3.2.2 pwm polarity ..................................................................................................... 24-15 24.3.2.3 pwm period and du ty ........................................................................................ 24-15 24.3.2.4 pwm timer count ers ......................................................................................... 24-16 24.3.2.5 left-aligned out puts .......................................................................................... 24-17 24.3.2.5.1 left-aligned output example ........................................................................ 24-17 24.3.2.6 center-aligned ou tputs ...................................................................................... 24-18 24.3.2.6.1 center-aligned out put example .................................................................... 24-19 24.3.2.7 pwm 16-bit functions ....................................................................................... 24-19 24.3.2.8 pwm boundary ca ses ........................................ ................................................ 24-21 chapter 25 flexcan 25.1 introducti on .............................................................................................................. ..... 25-1 25.1.1 block diagra m .......................................................................................................... 2 5-1 25.1.1.1 the can system .................................................................................................. 25-2 25.1.2 features ................................................................................................................ ..... 25-3 25.1.3 modes of operat ion .................................................................................................. 25-3 25.1.3.1 normal mode ........................................................................................................ 25- 3 25.1.3.2 freeze mode ......................................................................................................... 25 -3 25.1.3.3 module disabled mode ........................................................................................ 25-4 25.1.3.4 loop-back mode .................................................................................................. 25-4 25.1.3.5 listen-only m ode ............................................... .................................................. 25-5 25.2 external signal desc ription .......................................................................................... 25-5 25.3 memory map/register definition ................................................................................ 25-5 25.3.1 flexcan configurati on register (canmcr n ) ...................................................... 25-6 25.3.2 flexcan control register (canctrl n ) ............................................................... 25-8 25.3.3 flexcan free running timer register (timer n ) ............................................... 25-10 25.3.4 rx mask registers (rxgmask n , rx14mask n , rx15mask n ) ...................... 25-11 25.3.5 flexcan error counter register (errcnt n ) ...................................................... 25-12 25.3.6 flexcan error and status register (errstat n ) ................................................ 25-14
mcf5213 reference manual, rev. 1.1 xx freescale semiconductor preliminary contents paragraph number title page number 25.3.7 interrupt mask register (imask n ) ....................................................................... 25-16 25.3.8 interrupt flag register (iflag n ) .......................................................................... 25-16 25.3.9 message buffer st ructure ....................................................................................... 25-17 25.4 functional overvi ew ................................................................................................... 25-2 0 25.4.1 transmit process ..................................................................................................... 25- 21 25.4.2 arbitration proc ess ................................................. ................................................ 25-2 1 25.4.3 receive pro cess ...................................................................................................... 25- 22 25.4.3.1 self-received fr ames ......................................................................................... 25-23 25.4.4 matching proce ss .................................................................................................... 25-2 3 25.4.5 message buffer handling ....................................................................................... 25-23 25.4.5.1 serial message buff ers (smbs) ......................................................................... 25-23 25.4.5.2 message buffer deactivation ............................................................................. 25-24 25.4.5.3 locking and releasing me ssage buffers ........................................................... 25-24 25.4.6 can protocol relate d frames ............................................................................... 25-25 25.4.6.1 remote frames ................................................................................................... 25-25 25.4.6.2 overload fram es ................................................................................................. 25-26 25.4.7 time stamp ............................................................................................................. 2 5-26 25.4.8 bit timing .............................................................................................................. . 25-26 25.5 flexcan initializati on sequence ............................................................................... 25-28 25.5.1 interrupts .............................................................................................................. ... 25-29 chapter 26 debug module 26.1 introducti on .............................................................................................................. ..... 26-1 26.1.1 overview ................................................................................................................ ... 26-1 26.1.1.1 the new debug module hardwa re (rev. b+) ..................................................... 26-2 26.1.1.2 enhancements over revision a ............................................................................ 26-2 26.2 external signal desc ription .......................................................................................... 26-2 26.3 real-time trace support .............................................................................................. 26-3 26.3.1 begin execution of taken br anch (pst = 0x5) ....................................................... 26-5 26.4 memory map/register definition ................................................................................ 26-6 26.4.1 revision b+ shared de bug resources ..................................................................... 26-7 26.4.2 configuration/status re gister (csr) ........................................................................ 26-7 26.4.3 bdm address attribut e (baar) ............................................................................. 26-9 26.4.4 address attribute trigger register (aat r) .......................................................... 26-10 26.4.5 trigger definition regi ster (tdr) ......................................................................... 26-11 26.4.6 program counter breakpoint/mask registers (pbr, pbmr) ................................ 26-13 26.4.7 address breakpoint register s (ablr, abhr) ..................................................... 26-14 26.4.8 data breakpoint/mask regi sters (dbr, db mr) ................................................... 26-15 26.5 background debug mode (bdm) .............................................................................. 26-16
mcf5213 reference manual, rev. 1.1 freescale semiconductor xxi preliminary contents paragraph number title page number 26.5.1 cpu halt ................................................................................................................ . 26-16 26.5.2 bdm serial interface .............................................................................................. 26-17 26.5.2.1 receive packet format ....................................................................................... 26-18 26.5.2.2 transmit packet format ...................................................................................... 26-19 26.5.3 bdm command se t ................................................................................................ 26-19 26.5.3.1 coldfire bdm comma nd format ...................................................................... 26-21 26.5.3.1.1 extension words as required ......................................................................... 26-21 26.5.3.2 command sequence diagrams ........................................................................... 26-22 26.5.3.3 command set descri ptions ................................................................................ 26-23 26.5.3.3.1 read a/d register (rareg/rdreg) .................................................................... 26-23 26.5.3.3.2 write a/d register (wareg/wdreg) ................................................................ 26-24 26.5.3.3.3 read memory locat ion (read) ....................................................................... 26-24 26.5.3.3.4 write memory loca tion (write) ..................................................................... 26-26 26.5.3.3.5 dump memory block (dump) ........................................................................ 26-27 26.5.3.3.6 fill memory bloc k (fill) ................................................................................. 26-29 26.5.3.3.7 resume executio n (go) .................................................................................. 26-30 26.5.3.3.8 no operation (nop) ......................................................................................... 26-31 26.5.3.3.9 synchronize pc to the ps t/ddata lines (sync_pc) ................................... 26-31 26.5.3.3.10 read control regist er (rcreg) ......................................................................... 26-32 bdm accesses of the stack pointe r registers (a7: ssp, usp) 33 bdm accesses of the mac registers 33 26.5.3.3.11 write control regist er (wcreg) ...................................................................... 26-34 26.5.3.3.12 read debug module regist er (rdmreg) ......................................................... 26-35 26.5.3.3.13 write debug module regi ster (wdmreg) ....................................................... 26-36 26.6 real-time debug s upport .......................................................................................... 26-37 26.6.1 theory of oper ation ................................................................................................ 26-37 26.6.1.1 emulator mode ................................................................................................... 26-38 26.6.2 concurrent bdm and proc essor operation ............................................................ 26-39 26.7 processor status, ddata definition ......................................................................... 26-39 26.7.1 user instructi on set ................................................ ................................................ 26-4 0 26.7.2 supervisor instru ction set ....................................................................................... 26-44 26.8 freescale-recommende d bdm pinout ...................................................................... 26-44 chapter 27 ieee 1149.1 test access port (jtag) 27.1 introducti on .............................................................................................................. ..... 27-1 27.1.1 block diagra m .......................................................................................................... 2 7-1 27.1.2 features ................................................................................................................ ..... 27-2 27.1.3 modes of operat ion .................................................................................................. 27-2 27.2 external signal desc ription .......................................................................................... 27-2
mcf5213 reference manual, rev. 1.1 xxii freescale semiconductor preliminary contents paragraph number title page number 27.2.1 jtag enable (jta g_en) ........................................................................................ 27-2 27.2.2 test clock input (tclk) ......................................................................................... 27-3 27.2.3 test mode select/b reakpoint (tms/bkpt ) ............................................................. 27-3 27.2.4 test data input/development se rial input (tdi/dsi) ............................................. 27-3 27.2.5 test reset/developmen t serial clock (trst /dsclk) .......................................... 27-4 27.2.6 test data output/development se rial output (tdo/dso) ..................................... 27-4 27.3 memory map/register definition ................................................................................ 27-4 27.3.1 instruction shift regi ster (ir) .................................................................................. 27-4 27.3.2 idcode regist er ..................................................................................................... 27-4 27.3.3 bypass regi ster ......................................................................................................... 27-5 27.3.4 test_ctrl regist er .............................................................................................. 27-5 27.3.5 boundary scan regi ster ............................................................................................ 27-5 27.4 functional descri ption .................................................................................................. 27 -6 27.4.1 jtag module ........................................................................................................... 27 -6 27.4.2 tap controll er ......................................................................................................... 2 7-6 27.4.3 jtag instructi ons ..................................................................................................... 27 -7 27.4.3.1 idcode instruct ion ............................................................................................. 27-7 27.4.3.2 sample/preload inst ruction ......................................................................... 27-8 27.4.3.3 extest instruct ion ............................................................................................. 27-8 27.4.3.4 enable_test_ctrl in struction .................................................................... 27-8 27.4.3.5 highz instruct ion ................................................................................................ 27-8 27.4.3.6 clamp instruct ion .............................................................................................. 27-8 27.4.3.7 bypass instruc tion ........................................... .................................................. 27-8 27.5 initialization/applicati on informati on .......................................................................... 27-9 27.5.1 restricti ons ............................................................................................................ ... 27-9 27.5.2 nonscan chain op eration ......................................................................................... 27-9 appendix a register memory map
mcf5213 reference manual, rev. 1.1 freescale semiconductor xxiii preliminary review copy only about this book the primary objective of this reference manual is to define the functionality of the mcf5213 processor for use by software and hardware developers. in addition, this manual s upports the mcf5211 and mcf5212. this book is written from the perspective of the mcf5213, and unle ss otherwise noted, the information also applies to the mcf5211 and mcf5212. the mcf5211 and mcf5212 have the same functionality as the mcf 5213, and any differences in data regarding bus timing, signal behavior, and ac, dc, and thermal characteristics are in the data sheet. the information in this book is subjec t to change without notic e, as described in the disclaimers on the title page. as with any technical documentation, it is the reader?s responsibil ity to be sure he is using the most recent version of the documentation. to locate any published errata or updates for th is document, refer to the world-wide web at http://www.freesca le.com/coldfire . audience this manual is intended for system software and hardware developers and applications programmers who want to develop products with the mcf5213. it is assumed that the re ader understands operating systems, microprocessor system design, basic principles of software and hard ware, and basic details of the coldfire ? architecture. organization following is a summary and br ief description of the major sections of this manual: ? chapter 1, ?overview,? includes general descriptions of th e modules and features on the device, focusing in particul ar on new features. ? chapter 2, ?signal descriptions,? describes the device signals. it includes a listing of signals that characterizes each signal as an in put or output, defines its state at reset, and identifies whether a pull-up resistor should be used. ? chapter 3, ?coldfire core,? provides an overview of the micr oprocessor core. it describes the organization of the vers ion 2 (v2) coldfire processor core and includes an overview of the programming model as they ar e implemented on the device. ? chapter 4, ?hardware multiply/accumulate (mac) unit,? describes the multiply/accumulate (mac) unit, which executes inte ger multiply, multiply-accumulat e, and miscellaneous register instructions. the mac is integrated in to the operand execution pipeline (oep). ? chapter 5, ?static ram (sram),? covers general operations, conf iguration, and in itialization of the on-chip static ram (sram) implementation. it also provides information and examples of how to minimize power consum ption when using the sram. ? chapter 6, ?clock module,? describes the device?s different clocking methods. it also describes clock module operation in low power modes.
about this book mcf5213 reference manual, rev. 1.1 xxiv freescale semiconductor preliminary review copy only ? chapter 7, ?power management,? describes the low power operati on of the device and peripheral behavior in low power modes. ? chapter 8, ?chip configuration module (ccm),? details the various opera ting configurations of the device. it provides a description of signa ls used by the ccm and a programming model. ? chapter 9, ?reset controller module,? describes the operation of the reset controller module, detailing the different type s of reset that can occur. ? chapter 10, ?system control module (scm),? describes the functionality of the scm, which provides the programming model for peripheral acce ss control, the software core watchdog timer (cwt), and the generic access error information. ? chapter 11, ?general purpose i/o module ,? describes the operation a nd programming model of the general purpose i/o (gpi o) ports on the device. ? chapter 12, ?interrupt controller module,? describes operation of the interrupt controller portion of the scm. it includes descripti ons of the registers in the interr upt controller memory map and the interrupt priority scheme. ? chapter 13, ?edge port module (eport),? describes eport module functionality, including operation in low power mode. ? chapter 14, ?dma controller module,? describes the direct memory access (dma) controller module. it provides an overview of the module and describes in detail its signals and registers. the latter sections of this chapter describe operati ons, features, and supported data transfer modes in detail. ? chapter 15, ?coldfire flash module (cfm) ,? describes implementation of the superflash? technology licensed from sst used on this de vice. the coldfire flash module (cfm) is constructed with four banks of 32k x 16-bit flash to generate a 256- kbyte, 32-bit wide electrically erasable and programmable read- only memory array. the cfm is ideal for program and data storage for single-chip appli cations and allows for field reprogramming without external high-voltage sources. ? chapter 16, ?ezport ,? describes the interface that allows the flash memory contents on a 32 bit general purpose microcontroller to be read, erased and programme d from off-chip in a format compatible to many standalone flash memory chips. ? chapter 17, ?programmable interr upt timer modules (pit0?pit1),? describes the functionality of the pit timers, including operation in low power mode. ? chapter 18, ?general purpose timer module (gpt) ,? describes the functionality of the 4-channel general purpose timer module (gpt), including th e configuration of cha nnel 3 as a 16-bit pulse accumulator that can operate as a simple ev ent counter or as a gated time accumulator. ? chapter 19, ?dma timers (dtim0?dtim3) ,? describes the configur ation and operation of the four direct memory access (d ma) timer modules (dtim0, dt im1, dtim2, and dtim3). these 32-bit timers provide input capture and referenc e compare capabilities with optional signaling of events using interrupts or dma triggers. a dditionally, programming examples are included. ? chapter 20, ?queued serial peripheral interface (qspi),? provides a featur e-set overview and a description of operation, including de tails of the qspi?s internal storage organization. the chapter concludes with the programmi ng model and a timing diagram. ? chapter 21, ?uart modules,? describes the use of the universal asynchronous receiver/transmitters (uarts) implemented on the device and includes programming examples. ? chapter 22, ?i 2 c interface,? describes the i 2 c module, including i 2 c protocol, clock synchronization, and i 2 c programming model registers.
about this book mcf5213 reference manual, rev. 1.1 freescale semiconductor xxv preliminary review copy only ? chapter 23, ?analog-to-dig ital converter (adc) ,? describes the two separate and complete adcs, each with their own sample and hold circuits and a common voltage reference and common digital control module. ? chapter 24, ?pulse width modulation (pwm) module ,? describes the configuration and operation of the pulse width modulation (p wm) module. it includes a bloc k diagram, programming model, and functional description. ? chapter 25, ?flexcan ,? describes the implementation of the controller area network (can) protocol. it describes flexcan module operation and provides a programming model. ? chapter 26, ?debug module,? describes the hardware debug support in the device. ? chapter 27, ?ieee 1149.1 test access port (jtag),? describes configurati on and operation of the joint test action group (jtag) implementation. it describes those items required by the ieee 1149.1 standard and provides additional information sp ecific to the device. fo r internal details and sample applications, see the ieee 1149.1 document. ? appendix a, ?register memory map ,? summarizes the address, name, and byte assignment for registers within the cpu space, lists an overview of the memory map for the on-chip modules, and provides a detailed memory map including all of the registers for on-chip modules. additional literature is published as new processors become available. for a current list of coldfire documentation, refer to http://www.freescale.com/coldfire . conventions this document uses the foll owing notational conventions: cleared/set when a bit takes the valu e zero, it is said to be clea red; when it ta kes a value of one, it is said to be set. mnemonics in text, instruction mn emonics are shown in uppercase. mnemonics in code and tables, instruction mnemonics are shown in lowercase. italics italics indicate variable command parameters. book titles in text are set in italics. 0x0 prefix to denote hexadecimal number 0b0 prefix to denote binary number reg[field] abbreviations for regist ers are shown in uppercase. sp ecific bits, fields, or ranges appear in brackets. for example, rambar [ba] identifies the base address field in the ram base address register. nibble a 4-bit data unit byte an 8-bit data unit word a 16-bit data unit 1 longword a 32-bit data unit x in some contexts, such as signal encodings, x indicates a don?t care. n used to express an undefined numerical value ~ not logical operator 1. the only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. to simplify the discussion these un its are referred to as words regardless of length.
about this book mcf5213 reference manual, rev. 1.1 xxvi freescale semiconductor preliminary review copy only & and logical operator | or logical operator overbar an overbar indicates that a signal is active-low. register figure conventions this document uses the following convent ions for the register reset values: ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by th e polarity of the indicated signal. the following register fields are used: acronyms and abbreviations table i lists acronyms and abbreviati ons used in this document. r0 indicates a reserved bit field in a me mory-mapped register. these bits are always read as zeros. w r1 indicates a reserved bit field in a me mory-mapped register. these bits are always read as ones. w r fieldname indicates a read/write bit. w r fieldname indicates a read-only bit field in a memory-mapped register. w r indicates a write-only bit field in a memory-mapped register. w fieldname r fieldname write 1 to clear: indicates that writ ing a 1 to this bit field clears it. ww1c r0 indicates a self-clearing bit. w fieldname table i. acronyms and abbreviated terms term meaning adc analog-to-digital conversion alu arithmetic logic unit bdm background debug mode
about this book mcf5213 reference manual, rev. 1.1 freescale semiconductor xxvii preliminary review copy only bist built-in self test bsdl boundary-scan description language codec code/decode dac digital-to-analog conversion dma direct memory access dsp digital signal processing ea effective address fifo first-in, first-out gpio general-purpose i/o i 2 c inter-integrated circuit ieee institute for electrical and electronics engineers ifp instruction fetch pipeline ipl interrupt priority level jedec joint electron device engineering council jtag joint test action group lifo last-in, first-out lru least recently used lsb least-significant byte lsb least-significant bit mac multiply accumulate unit, also media access controller mbar memory base address register msb most-significant byte msb most-significant bit mux multiplex nop no operation oep operand execution pipeline pc program counter pclk processor clock plic physical layer interface controller pll phase-locked loop por power-on reset pqfp plastic quad flat pack pwm pulse width modulation table i. acronyms and abbreviated terms (continued) term meaning
about this book mcf5213 reference manual, rev. 1.1 xxviii freescale semiconductor preliminary review copy only terminology conventions table ii shows terminology conventions used throughout this document. qspi queued serial peripheral interface risc reduced instruction set computing rx receive sim system integration module sof start of frame tap test access port ttl transistor transistor logic tx transmit uart universal asynchronous/synch ronous receiver transmitter table ii. notational conventions instruction operand syntax opcode wildcard cc logical condition (example: ne for not equal) register specifications an any address register n (example: a3 is address register 3) ay,ax source and destination address registers, respectively dn any data register n (example: d5 is data register 5) dy,dx source and destination data registers, respectively rc any control register (example vbr is the vector base register) rm mac registers (acc, mac, mask) rn any address or data register rw destination register w (us ed for mac instructions only) ry,rx any source and destination registers, respectively xi index register i (can be an address or data register: ai, di) miscellaneous operands # immediate data following the 16-bit operation word of the instruction effective address y,x source and destination effective addresses, respectively table i. acronyms and abbreviated terms (continued) term meaning
about this book mcf5213 reference manual, rev. 1.1 freescale semiconductor xxix preliminary review copy only


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